As a non-volatile semiconductor memory device, Patent Document 1, for example, proposes a configuration as shown in FIG. 9. Referring to FIG. 9, in this non-volatile semiconductor memory device, a channel is formed between n+ diffusion regions (heavily doped n+ regions) 107 and a buried-type common diffusion region 121. Then, by trapping electric charge in charge trap sites (storage nodes) formed of an ONO film (constituted from an oxide film, nitride film, and an oxide film) on both sides of a cell, two-bit information per cell can be independently written, read, and erased. The n+ diffusion regions 107 are formed in the surface of a substrate and constitute bit lines. Referring to FIG. 9, reference numeral 101 denotes a memory cell area formed of a p well (termed a memory cell diffusion layer area). Reference numeral 103 denotes select gates (select gates). Reference numeral 111 denotes word lines that cross the select gates 103 and are disposed over the select gates 103 through an insulating film. Reference numeral 116 denotes bit lines on a first metal interconnect layer (a first aluminum interconnect layer). Reference numerals 200A and 200B on both sides of a memory cell area denote bank selecting sections. The select gates 103 are alternately extended from one side of the memory cell area and the other side opposite to the one side to the opposing other side and the opposing one side.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2004-71646A